asic verification engineer
2 days ago
Key Responsibilities:
- Develop and execute verification plans for ASIC designs based on specifications and requirements.
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- Design and implement testbenches using SystemVerilog or other verification languages.
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- Create reusable verification components and environments using UVM (Universal Verification Methodology).
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- Perform functional verification, including simulation, debugging, and regression testing.
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- Work closely with the design team to identify and resolve bugs and design issues.
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- Collaborate on coverage analysis and closure to ensure thorough verification of all functionalities.
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- Contribute to the development of automated verification flows and methodologies.
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- Document verification processes and results, providing regular updates to project stakeholders.
Qualifications:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
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- Proven experience in ASIC verification, including testbench development and simulation.
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- Strong knowledge of SystemVerilog and UVM.
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- Familiarity with ASIC design flows, EDA tools, and simulation tools such as VCS, Questa, or Cadence Xcelium.
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- Hands-on experience with functional coverage and assertion-based verification.
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- Solid understanding of digital design and hardware description languages (HDLs) like Verilog or VHDL.
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- Strong debugging skills and proficiency in scripting languages such as Python, Perl, or TCL.
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- Effective communication and teamwork skills.
Preferred Skills:
- Experience in low-power verification methodologies.
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- Knowledge of formal verification techniques.
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- Familiarity with high-speed interfaces (e.g., PCIe, DDR, Ethernet).
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- Exposure to post-silicon validation processes.
Why Join Us?
- Be part of a dynamic team working on cutting-edge ASIC projects.
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- Opportunity to contribute to innovative silicon solutions across diverse applications.
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- Competitive compensation and benefits package.
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