Formal Verification Engineer
4 days ago
We are hiring Formal Verification Engineer for the position based in Stockholm, Sweden (Remote).
Educational Qualification: Bachelor's degree in Computer Science, Engineering, or a related field.
Job Summary:
We are seeking a highly skilled Formal Verification Engineer who will be responsible for formal verification of digital design components to ensure functional correctness and to identify design issues early in the development process. You will work with modern verification tools and methodologies to improve verification coverage and efficiency.
Required Experience/Competences:
- 5-6+ years of experience in formal verification within ASIC design.
- Strong understanding of digital design and hardware description languages such as System Verilog.
- Proven experience in UVM (Universal Verification Methodology) for efficient testbenches and verification processes.
- Expertise in formal verification tools and methodologies used in the industry.
Soft Skills:
- Excellent analytical and problem-solving skills to troubleshoot and resolve verification issues.
- Strong ability to collaborate effectively with cross-functional teams, including design and verification engineers.
- Independent and proactive approach to work, with a focus on continuous improvement of verification strategies.
- Ability to communicate complex verification issues clearly to technical and non-technical stakeholders.
Job Category: Hardware
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