UVM Verification Engineer

4 weeks ago


Stockholm, Stockholm, Sweden Microtech Global Ltd Full time
Job Overview

Job Title: UVM Verification Engineer

Duration: 12 months

Location: Remote

Remote Work: Up to % available

We are seeking a skilled Verification Engineer to support the design and verification of our client's next-generation Machine Learning IP. As a key member of our team, you will leverage your expertise in UVM and SystemVerilog to ensure the highest quality verification of our IP.

Key Responsibilities
  1. Develop and execute comprehensive verification plans to minimize bug escapes and ensure high-quality results
  2. Design and implement coverage-driven verification strategies for high-complexity designs
  3. Collaborate with cross-functional teams to plan and execute verification processes
  4. Develop and debug SystemVerilog/UVM constrained-random testbenches
  5. Estimate and manage verification effort and timelines
Requirements
  1. Strong discipline and attention to detail in ensuring effective high-quality verification
  2. Expertise in coverage-driven verification and high-complexity design verification
  3. Experience in block-level, top-level, and system-level verification
  4. Proficiency in Verilog, SystemVerilog, and VHDL
  5. Experience in planning and executing verification processes

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