
Experienced Verification Professional for Telecommunications
2 days ago
Role Summary:
We are seeking an experienced verification engineer to join our ASIC IP team and contribute to the development of cutting-edge technologies. The successful candidate will have a strong background in ASIC or FPGA verification at IP, sub-system, and chip levels, using SystemVerilog UVM, and experience designing UVM test environments and driving coverage closure.
Key Responsibilities:
- Develop a comprehensive verification plan, including specifications.
- Architect and enhance state-of-the-art verification environments.
- Implement and maintain UVCs, ensuring every corner of the design is verified.
- Drive both random and directed testing strategies to uncover hidden bugs.
- Leverage advanced coverage techniques to ensure top-tier verification completeness.
Requirements:
- Expertise in ASIC or FPGA verification at IP, sub-system, and chip levels, using SystemVerilog UVM.
- Experience designing UVM test environments and driving coverage closure.
- A Master's degree in Electrical Engineering, Computer Engineering, or a related field.
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