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2 weeks ago
We are seeking a highly skilled and experienced Formal Verification Specialist with a minimum of 5 years of industry experience, focusing on formal techniques for verification.
The ideal candidate will possess deep knowledge of architectures of designs and digital logic, synthesis flow, static timing flows, and formal checking.
- Specifying, implementing, and maintaining an integrated end-to-end formal verification flow for the formal verification objective.
- Guiding and training team members on effective usage of FV tools.
- Reviewing formal setups and proofs with design and verification teams.
- Maintaining and extending assertion libraries, including support for both simulation and formal verification.
- Identifying key behaviors for verification of DUT and creating a formal verification plan.
- Developing verification environments, including environmental assumptions, assertions, and cover properties in the context of the verification plan.
- Strong knowledge of architectures of designs and digital logic.
- Experience with synthesis flow and static timing flows, formal checking, etc.
- Hands-on experience with HDLs such as Verilog / System Verilog.
- Understanding of temporal logic assertions.
- Experience with at least one formal verification tool (e.g., Jasper, VC-Formal).
- Experience with complex verification projects that used formal techniques for closure.
