Senior Formal Verification Engineer

2 days ago

Solna Municipality, Sweden Swedium Global Services AB Full time
Swedium Global is the growing System Engineering and Solution Company, offers services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy and Outsourcing services to our clients across the globe for an onsite and offshore business model. Swedium Global is having presence in Sweden, Finland, Poland, Czech Republic and in India.

Location: Sweden

Expected Start date: ASAP

Job Name: Senior Formal Verification Engineer

You are a highly skilled and experienced Formal Verification Specialist. You have a minimum of 5 years of industry experience, with at least the last 4 years focused on formal techniques for verification. You possess deep knowledge of architectures of designs and digital logic, synthesis flow, static timing flows, and formal checking. Your hands-on experience with HDLs such as Verilog or System Verilog and understanding of temporal logic assertions make you an ideal candidate for this role. You have worked on complex verification projects and have experience with formal verification tools like Jasper or VC-Formal. Your skills in Python, Perl, or Shell scripting are a plus.

What You'll Be Doing:

* Specifying, implementing, and maintaining an integrated end-to-end formal verification flow for the formal verification objective.

* Guiding and training team members on effective usage of FV tools.

* Reviewing formal setups and proofs with design and verification teams.

* Maintaining and extending assertion libraries, including support for both simulation and formal verification.

* Identifying key behaviors for verification of DUT and creating a formal verification plan.

* Developing verification environments, including environmental assumptions, assertions, and cover properties in the context of the verification plan.

* Applying various formal verification techniques to prove the correctness of digital designs.

* Debugging RTL to identify causes of failure scenarios.

What You'll Need:

* Strong knowledge of architectures of designs and digital logic.

* Experience with synthesis flow and static timing flows, formal checking, etc.

* Hands-on experience with HDLs such as Verilog / System Verilog.

* Understanding of temporal logic assertions.

* Experience with at least one formal verification tool (e.g., Jasper, VC-Formal).

* Experience with complex verification projects that used formal techniques for closure.

* Skills in Python, Perl, or Shell scripting (a plus).

Careers@swediumglobal.com

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