
Senior ASIC Design Verification Lead
6 days ago
Overview
\Swedium Global is a pioneer in the field of semiconductor engineering and solution provision, catering to clients across the globe with its onsite and offshore business model.
\Our presence in Sweden, Finland, Poland, Czech Republic, and India enables us to deliver customized solutions tailored to client needs.
\Job Role
\We are looking for a seasoned verification expert to spearhead the development of cutting-edge IPs for 5G and 6G technologies. The successful candidate will be responsible for creating and implementing verification strategies, designing and enhancing verification environments, and driving continuous improvement in product quality and efficiency.
\Key Responsibilities
\Develop comprehensive verification plans, including specifications and requirements.
Design and enhance state-of-the-art verification environments.
Implement and maintain UVCs to ensure thorough design verification.
Drive both random and directed testing strategies to uncover hidden bugs and improve overall verification completeness.
Leverage advanced coverage techniques to ensure top-tier verification completeness.
Requirements
\The ideal candidate will possess expertise in ASIC or FPGA verification at IP, sub-system, and chip levels, using SystemVerilog UVM. They should have hands-on experience designing UVM test environments and driving coverage closure, along with a Master's degree in Electrical Engineering, Computer Engineering, or a related field.
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