Chief Verification Architect

At Swedium Global Services AB, we are a growing System Engineering and Solution Company offering various services like Semiconductor Engineering R&D, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy and Outsourcing services to our clients globally. Our presence spans across Sweden, Finland, Poland, Czech Republic, and India.

• We seek an experienced Formal Verification Specialist with a minimum of 5 years industry experience focusing on formal techniques for verification.

The ideal candidate possesses deep knowledge of architectures of designs and digital logic, synthesis flow, static timing flows, and formal checking. Hands-on experience with HDLs such as Verilog or System Verilog and understanding of temporal logic assertions make this person an ideal fit. Experience with formal verification tools like Jasper or VC-Formal is required.

The successful candidate has worked on complex verification projects and can identify key behaviors for verification of DUT and create a formal verification plan. They will develop verification environments, including environmental assumptions, assertions, and cover properties in the context of the verification plan. This individual will also apply various formal verification techniques to prove the correctness of digital designs and debug RTL to identify causes of failure scenarios.

1. Specifying, implementing, and maintaining an integrated end-to-end formal verification flow for the formal verification objective.
2. Guiding and training team members on effective usage of FV tools.
3. Reviewing formal setups and proofs with design and verification teams.
4. Maintaining and extending assertion libraries, including support for both simulation and formal verification.
5. Identifying key behaviors for verification of DUT and creating a formal verification plan.
6. Developing verification environments, including environmental assumptions, assertions, and cover properties in the context of the verification plan.
7. Applying various formal verification techniques to prove the correctness of digital designs.
8. Debugging RTL to identify causes of failure scenarios.