Senior ASIC Verification Engineer
1 month ago
For our client we are looking for a Senior ASIC Verification Engineer
Responsibilities & Tasks
• Define and implement UVM based test environments for IPs and subsystem.
• Develop, run and debug testcases.
• Usage of uVC´s
• Development of uVC´s (if needed)
• Usage of reference models (if needed)
• Constrained random testing
• Creation of Coverage matrix
• Writing Verification Report
Requirements
• Several years’ experience in verification using System Verilog and UVM
• Knowledge of Verilog/VHDL
• Knowledge of Object-Oriented Programming concepts
• Experience in developing test plans and directed/randomized test cases from scratch
• Experience in formal verification
• Experience with simulation verification tools (Mentor/Cadence)
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