ASIC Verification Engineer
4 weeks ago
We are looking for an experienced IP verification engineering in a team developing the Serdes subsystem and its IPs for our customer. Most of the verification uses constrained random methodology but also dedicated test-vectors and assertions are used.
The work includes:
- Development of UVM testbenches and test cases for IPs.
- Debugging of test environment and design
- Creation of Scoreboards
- Refinement of assertions and coverage
- Creation of relevant documentation
Location: Lund
Requirements
- Advanced user of System Verilog
- Advanced user of UVM tools and methodology for IP verification.
- Significant experience in assertions, scoreboards and coverage refinement
Requirements
Advanced user of System Verilog Advanced user of UVM tools and methodology for IP verification. Significant experience in assertions, scoreboards and coverage refinement
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